Phase detectors are logic circuits used to generate pump-up and pump-down signals to control charge-pump circuits in a clock and data recovery PLL. Phase detectors can also generate recovered-data. As operating speeds of clock and data recovery units increase, the design of voltage-controlled oscillators and charge pump circuits becomes complicated and highly power consuming. Current architectures use full-rate clocks and tend to generate nominally half-bit-wide pump-up and pump-down pulses. This implies that charge-pump must work with narrow pulses. However, it is desirable to have nominally bit-wide pump-up and pump-down pulses. Some architectures use multiple phases of a lower-rate clock but feature non-linear characteristics or reduced linear range.
Referring to FIG. 1, a circuit 10 illustrates a conventional phase detector that may be found in U.S. Pat. No. 5,712,580. The circuit 10 comprises a number of D flip-flops 12a-12n, a delay circuit 14, a delay circuit 16, an XOR gate 18 and a OR gate 20.
The phase detector 10 generates a one and one-half bit wide pump-up and pump-down signal. However, the phase detector 10 works on every other rising (or falling) data edge only. As a result, to generate a set of pump signals for every edge of data, the basic phase detector structure must be replicated four times (twice for each rising edge and twice for each falling edge). The phase detector 10 may require an excessive number of gates due to the replication of the circuit four times to retain information in all data edges. The additional gates imply more power consumption.